1. Fied of the Invention
This invention relates to semi-custom semiconductor logic integrated circuit devices, and more particularly to standard-cell type gallium arsenide large scale integrated circuit devices.
2. Description of the Related Art
With an increase in the performance and reliability of large scale digital systems, the technique for forming highly integrated electronic parts such as ICs and LSIs becomes indispensable. In particular, with the recent development of computer technology, semiconductor logic LSIs have made remarkable progress in both the integration density and performance thereof. Also, semi-custom semiconductor logic integrated circuit devices are not an exception. In general, it is safe to say that standard-cell type logic devices are dominant among semi-custom logic LSIs for semiconductor device manufacturers.
The standard-cell type logic device has standard circuits of previously selected types formed on a substrate. The standard circuits are previously selected from those registered in a library in order to attain a desired LSI logic function. An internal circuit design of the logic devices is typically made by using an automatic designing tool such as a computer-aided design (CAD). The automatic design of the internal circuit is effected by wiring a large number of standard circuits according to an adequate routing algorithm. When the internal wiring design is completed, a logic device of a desired function can be obtained.
However, presently available standard-cell type logic devices have a problem that there is a limitation of possibility for increasing both the integration density and the operation reliability thereof at the same time as will be described in detail hereinafter. In general, with this type of semi-custom logic device, the standard circuits are constructed by direct-coupled FET logic circuits having gallium arsenide (GaAs) logic gates. The direct-coupled FET logic gate circuits (which are hereinafter referred to as "DCFL circuits" according to the practice in this technical field) have no level-shift stages. Therefore, since the number of circuit constituting elements for each unit gate is small, a larger number of DCFL circuits can be laid out on the chip substrate of a limited size. This is advantageous in increasing the integration density of the standard-cell type logic device.
In contrast, the logic swing width of DCFL circuits may be set as low as approx. 0.6 volts without the level-shift stage. The small logic amplitude is advantageous from the viewpoint of increase in the operation speed. However, it causes a great obstacle to the enhancement of the operation reliability of the standard-cell type logic device. This is because the small logic swing width reduces the noise margin of the DCFL circuit and increases the rate of occurrence of logic operation error.
The DCFL standard circuits of the standard-cell type logic device include some standard cells. Each of the standard cells is connected with power supply lines. The power supply lines are a ground line and a power source voltage supply line. Where the power supply lines are formed to connect the DCFL standard circuits which are separately formed on the chip substrate on the entire portion of the substrate, then the total length of the power supply lines may be substantially the same as that of other ordinary signal transmission wirings. Since MESFETs are generally used for standard cells in GaAs-LSIs, small dissipation currents flow in all of the standard cells, so that the actual ground potential of the ground line is raised from an ideal 0 volt and becomes unstable. The "instability" phenomenon of the ground potential becomes significant in an area which is far apart from external connection pads of the chip substrate or the central area of the chip wirings, and as a result, the effective logic swing width of the DCFL standard circuits is lowered accordingly. If the logic amplitude is originally set as low as 0.6 volts, the effective amplitude is further lowered. This not only reduces the noise margin but also extremely degrades the stability of the logic operation. As a result, the operation reliability of the standard-cell type logic device is lowered.
Occurrence of the "instability" phenomenon of the ground potential may be suppressed to some extent by making the power supply lines thicker to lower the wiring resistance; however, in this case, the area of the power supply lines increases, deteriorating the feature of high integration density which can be attained as the inherent merit of the DCFL standard circuit.